Assistant Professor
Electronics & Communication Engineering
NIT Warangal
5 years
VLSI Design, EDC, Digital Logic Design, IC Fabrication Techniques, Linear IC applications, Digital IC design, CMOS VLSI
Circular gate MOSFETs, Novel Semiconductor Devices Modeling and Simulation, Multi gate MOSFETs, Non-standard layout MOSFETs, Radiation Effects on MOSFETs.
Ph.D (Full Time) in Electronics & Communication Engineering from National Institute of Technology, Warangal (2018-23)
M.Tech in VLSI & Embedded Systems from KITS, Warangal, Affiliated College of Kakatiya University, Warangal (2011-13)
B.Tech in Electronics & Communication Engineering from Affiliated College of JNTU Hyderabad (2006-10)
Assistant Professor at SR University, from 2023-05-04 to Till Date.
Assistant Professor at Nalla Malla Reddy engineering College (NMREC), Hyderabad, from 2017-07-01 to 2018-10-30.
Assistant Professor at Warangal Institute of Technology and Science (WITS), Warangal, from 2013-12-09 to 2017-06-28.
PG
UG
K.Sagar and M.Satish, “Benchmarking and Optimization of Circular Double Gate MOSFET (CDGT) for Sub 10 nm Nodes,” Silicon 15, 3549–3558 (2023). https://doi.org/10.1007/s12633-022-02282-6 (SCI). Impact factor = 3.4 H- Index = 41
K.Sagar and M.Satish, “A Novel Vertically Stacked Circular Nanosheet FET for High Performance Applications,” ECS J. Solid State Sci. Technol., (2022) https://doi.org/10.1149/2162-8777/ac71c9(SCI). Impact factor = 2.2 H- Index = 77
K. Sagar and M. Satish, “Performance analysis of sub 10nm double gate Circular / Ring MOSFET,” Silicon, pp. 1–9, 2022, (2022) https://doi.org/10.1007/s12633-022-01668-w (SCI). Impact factor = 3.4 H- Index = 41
S. Kallepelli and S. Maheshwaram, “A novel circular double gate with raised source/drain SOI MOSFET,” Semicond. Sci. Technol., vol. 36, no. 6, p. 65009, 2021, (2021) https://doi.org/10.1088/1361-6641/abf0e6. (SCI) Impact factor = 2.361 H- Index = 122
K. Sagar and M. Satish, "Performance Comparison of Circular Double Gate Transistor (CDGT) with Novel Architectures for High-Performance Applications," 2022 IEEE International Symposium on Smart Electronic Systems (iSES), Warangal, India, 2022, pp. 148-152, (2023) doi: 10.1109/iSES54909.2022.00039. (SCOPUS)
K. Sagar, “An Alternative Logic Approach to Implement Energy Efficient 90-Nm Cmos Full Adders” International Journal of Scientific Research, Oct 2013. (2013) https://doi.org/10.36106/ijsr. (SCOPUS)
I received JRF (Junior Research Fellowship) award letter from MHRD (UGC-NET) in AUG-2017
I have qualified UGC-NET (NATIONAL ELIGIBILITY TEST) Assistant Professor in JULY-2016.
I have qualified UGC-NET (NATIONAL ELIGIBILITY TEST) Assistant Professor in DECEMBER-2015.
Stood as KAKATIYA UNIVERSITY(KU) Topper received Rank Certificate in M. Tech (VLSI&ES)
Stood as college topper & received GOLD Medal in M. Tech (VLSI&ES) in KITS Warangal.
I have qualified GATE-2018 with rank of 3866
I have qualified GATE-2016
I have qualified GATE-2013
I have qualified GATE-2011
